Electrochemical deposition is used for sophisticated packaging and multichip interconnection technologies known generally as through silicon via (TSV) and wafer level packaging (WLP) electrical connection technology. These technologies present significant challenges.
Generally, the processes of creating TSVs are loosely akin to damascene processing but are conducted on recessed features that are larger and have higher aspect ratios. In TSV processing, a cavity or a recess is first etched into a substrate (e.g. a silicon wafer); next a dielectric liner may be formed on both the internal surface of the recessed feature and the field region of the substrate; then both the internal surface of the recessed feature and the field region of the substrate are metallized with a diffusion barrier and/or adhesion layer (e.g. Ta, Ti, TiW, TiN, TaN, Ru, Co, Ni, W), and an “electroplateable seed layer” (e.g. Cu, Ru, Ni, Co, that can be deposited, for example, by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or electroless plating processes). Next, the metallized recessed features are filled with metal using, for example, “bottom up” copper electroplating. Note that the dielectric liner may not be deposited for substrates that are not electrically conductive such as for a glass, sapphire, or polymer substrate.
In contrast, through resist WLP feature formation typically proceeds differently. The process typically starts with a substantially planar substrate that may include some low aspect ratio vias or pads. The substantially planar dielectric substrate is coated with an adhesion layer followed by a seed layer (typically deposited by PVD). Then a photoresist layer is deposited and patterned over the seed layer to create a pattern of open areas in which the seed layer is exposed. Next, metal is electroplated into the open areas to form a pillar, line, or another feature on the substrate, which, after stripping the photoresist, and removing the seed layer by etching, leaves various electrically isolated embossed structures over the substrate.
Both of these technologies (TSV and through resist plating) require electroplating on a significantly larger size scale than damascene applications. Depending on the type and application of the packaging features (e.g. through chip connecting TSV, interconnection redistribution wiring, or chip to board or chip bonding, such as flip-chip pillars), plated features are often greater than about 2 micrometers in diameter and may be about 5 to about 100 micrometers in diameter (for example, pillars may be about 50 micrometers in diameter). For some on-chip structures such as power busses, the feature to be plated may be larger than 100 micrometers. The aspect ratios of the through resist WLP features are typically about 2:1 (height to width) or lower, more typically 1:1 or lower, while TSV structures can have very high aspect ratios (e.g., about 10:1 or 20:1).